Research

My work sits at the boundary between compilers and hardware. I build systems that reason formally about runtime behavior at compile time: a profiler that measures how long data actually lives inside an accelerator, and a compiler framework that turns those measurements into a provably optimal placement schedule across heterogeneous memory. The systems themselves are described on the Projects page; this page covers the research context and the publication record.

Memory Systems for AI Accelerators: LtRAM and StRAM

September 2024 – March 2026

For the first part of my Ph.D. my primary research direction was memory systems for domain-specific hardware accelerators, in collaboration with researchers across the Computer Science and Electrical Engineering departments at Stanford. This work was carried out within the Differentiated Access Memories (DAM) project, a multi-year Stanford effort to define how future computers will manage memory as a heterogeneous resource with different tradeoffs. My involvement in that project ended in March 2026.

I was interested in the “memory wall” problem in the AI and ML fields, where the surging size of AI models demands more on-chip memory to store intermediate results. Even as logic continues to scale down with more advanced process nodes, the density of SRAM has not kept pace, creating the risk that memory comes to dominate the area and power budgets of future AI accelerators. That points to renewed interest in alternative on-chip memory devices offering higher density and better fJ/bit efficiency.

We argued that memory will evolve from a uniform address space into a heterogeneous collection of devices optimized for different uses. The questions this direction sought to answer: what new memory technologies will we need, how do we compose them in systems, and what caching mechanisms do they need? How can applications and algorithms guide the composition of heterogeneous memories? How will software present and manage them?

My contributions to this direction, chronologically:

Current Direction

Fall 2026

Through the Fall 2026 academic quarter I am rotating with Prof. Keith Winstein, reading into deterministic and content-addressed computation, distributed dataflow and task-graph execution, and the formal semantics of program execution. I am interested in how deterministic dependencies, memoization, and precise evaluation rules might support operator fusion, symbolic execution, and termination prediction at the compiler level.

Undergraduate-level Research

Most of my research experience prior to Stanford was at the University of Michigan, through the Civil and Environmental Engineering department and the University of Michigan Transportation Research Institute (UMTRI).

Road-side based cybersecurity in connected and automated vehicle systems, January 2022 – April 2024

This project encompassed my research work done under the guidance of Prof. Neda Masoud at the University of Michigan Center for Connected and Automated Transportation. The overarching objective of the project was “to develop a holistic framework that integrates physics-based data-driven modeling and dynamic decision making under uncertainty and partial information to improve cybersecurity in connected and automated vehicles (CAV).”

UMTRI Bioscience Group, February 2022 – August 2022

I worked as a research assistant at the University of Michigan Transportation Research Institute's Biosciences Group over the Winter, Spring, and Summer 2022 terms. The group “conducts research on the biomechanics of motor vehicle occupants as it relates to occupant injuries, crash protection, and occupant accommodation.”

Publications, Preprints and Conference Presentations

You can also find my articles on my Google Scholar profile.

LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation

Published in arXiv preprint, 2026

A benchmark of 1,000 automatically generated, correct-by-construction problems that measures how well large language models recover finite-state machine behavior from natural-language specifications and translate it into correct RTL.

Recommended citation: Yuheng Wu, Berk Gokmen, Zhouhua Xie, Peijing Li, Caroline Trippel, Priyanka Raina, and Thierry Tambe. 2026. LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation. https://doi.org/10.48550/arXiv.2602.07032
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Towards Memory Specialization: A Case for Long-Term and Short-Term RAM

Published in Workshop on Disruptive Memory Systems (DIMES 25), 2025

A paradigm shift from simple memory hierarchies toward specialized memory architectures that exploit application-specific access patterns, proposing long-term RAM (LtRAM) and short-term RAM (StRAM).

Recommended citation: Peijing Li, Muhammad Shahir Abdurrahman, Rachel Cleaveland, Sergey Legtchenko, Philip Levis, Ioan Stefanovici, Thierry Tambe, David Tennenhouse, Caroline Trippel, and H.-S. Philip Wong. 2025. Towards Memory Specialization: A Case for Long-Term and Short-Term RAM. In Workshop on Disruptive Memory Systems (DIMES '25), October 13, 2025. Association for Computing Machinery, Seoul, Korea (South), 10. https://doi.org/10.1145/3764862.3768175
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The Future of Memory: Limits and Opportunities

Published in Workshop on Big Memory Systems (BigMem 25) at SOSP, 2025

A reconsideration of proposed system architectures with huge shared memories, arguing instead for breaking memory into smaller slices tightly coupled with compute elements.

Recommended citation: Samuel Dayo, Shuhan Liu, Peijing Li, Philip Levis, Subhasish Mitra, Thierry Tambe, David Tennenhouse, and H.-S. Philip Wong. 2025. The Future of Memory: Limits and Opportunities. https://doi.org/10.48550/arXiv.2508.20425
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GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition

Published in arXiv preprint, 2025

The first comprehensive, open-source framework that aligns dynamic, fine-grained workload lifetime profiles with memory device characteristics to enable generation of optimal StRAM memory compositions.

Recommended citation: Peijing Li, Matthew Hung, Yiming Tan, Konstantin Hoßfeld, Jake Cheng Jiajun, Shuhan Liu, Lixian Yan, Xinxin Wang, Philip Levis, H.-S. Philip Wong, and Thierry Tambe. 2025. GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition. https://doi.org/10.48550/arXiv.2504.14866
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OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads

Published in arXiv preprint, 2025

An open-source GCRAM compiler capable of generating GCRAM bank circuit designs and DRC- and LVS-clean layouts for commercially available foundry CMOS.

Recommended citation: Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, and H.-S. Philip Wong. 2025. OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads. https://doi.org/10.48550/arXiv.2507.10849
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A Communication Protocol for Securing Connected Vehicle Platoons Using Joint Hardware-Software Means

Published in 2023 Global Symposium on Mobility Innovation Presented by Mcity and UMTRI, 2023

Poster presentation proposing a novel protocol for authenticating and securing communication within connected vehicle platoons.

Recommended citation: Peijing Li and Neda Masoud. 2023. A communication protocol for securing connected vehicle platoons using joint hardware-software means. In 6th Student Poster Competition at the CCAT Global Symposium, April 05, 2023. Center for Connected and Automated Transportation, Ann Arbor, MI. Retrieved from https://ccat.umtri.umich.edu/symposium/2023-symposium/#poster
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