I build tools that make hardware and compiler decisions measurable and provable, from data-lifetime profiling to solver-backed memory placement.
I am a Ph.D. student in Electrical Engineering at Stanford University, entering my third year in Fall 2026, and I am simultaneously completing an M.S. in Electrical Engineering, expected in December 2026. Before Stanford I received my B.S.E. in Computer Science, with a minor in Civil Engineering, from the University of Michigan in 2024, summa cum laude.
Resume (PDF) · CV · peli@stanford.edu
Research
My work sits at the boundary between compilers and hardware. I build systems that reason formally about runtime behavior at compile time: GainSight, a profiler that measures how long data actually lives inside an accelerator, and Flan, a compiler framework that turns those measurements into a provably optimal placement schedule across heterogeneous memory. The same lifetime measurements drive the refresh policy of an embedded DRAM controller I designed for a 16nm accelerator tapeout, which is where the analysis stops being a simulation result and becomes silicon.
The motivating observation is that most accelerator memory accesses are extremely short-lived, so memory provisioned to retain data for milliseconds is overprovisioned for nearly everything it holds. That argument is set out in the position paper “Towards Memory Specialization: A Case for Long-Term and Short-Term RAM” (DIMES '25).
Through the Fall 2026 academic quarter I am rotating with Prof. Keith Winstein, reading into deterministic and content-addressed computation and the formal semantics of program execution. This is exploratory: it is a direction I am studying, not one I have published in.
See the Projects page for the systems I have built, the Research page for papers and prior research directions, and the Academics page for coursework and academic projects.
Experience
- AI Hardware Research Intern, TSMC Corporate Research (Summer 2026, San Jose, CA) — I extended an in-house analytical model for ASIC and GPU performance so that it supports workload profiling for large language model inference, and investigated embedded DRAM opportunities across activations, KV cache, and weights. I also built an analytical cost model for multi-chip scaling behavior, unifying several interconnect topology families under a single latency and energy notation.
- Head Teaching Assistant, Stanford CS 217 (Winter 2026) — CS 217: Hardware Accelerators for Machine Learning had not been offered since Winter 2022. Together with three other teaching assistants and two faculty instructors, I rebuilt it from the ground up, and enrollment reached roughly 100 students against an expected 40 to 60. I authored the lab sequence in which students build a large language model accelerator one component per assignment, including a systolic array, a memory hierarchy, and a compiler backend, culminating in an open-ended final project. All starter code was written from scratch; the SystemC and Verilog accelerator code was adapted from my own 16nm tapeout with the block floating-point and microscaling formats removed. Lab turnaround time on FPGA was the binding constraint, so I tuned DSP utilization for the arithmetic circuits through Siemens Catapult and Xilinx Vivado until it was tractable. I also designed the final-project rubric and gave in-person feedback on every project proposal.
- Software Test Engineer Intern, ASML (Summer 2023, San Jose, CA) — I owned the automation of nightly regression triage for focus-exposure modeling software. The suite ran roughly 300 test cases over about six hours, and attributing each failure to a commit and an owner cost two to three hours every day, spread across a five-engineer team. Afterwards it ran unattended in five to ten minutes and emailed my supervisor a summary of failing tests with their owners, leaving a human only the triage decision. The scripts outlasted the internship and are still a maintained part of the team's workflow three years later.
- Instructional Aide, University of Michigan (Winter 2023) — I ran weekly lab sections for CEE 375: Sensors, Circuits, and Signals, where students built sensing and signal-processing circuits on breadboards with Arduino and MATLAB. Bridging my students' civil-engineering background with the electrical-engineering concepts in the course was especially rewarding.
- Software Engineering Intern, Dell EMC (Summer 2021, Shanghai, China) — I automated lifecycle-management validation for VxRail hyperconverged infrastructure across the Kubernetes interface, the VMware ESXi hypervisor, and the VMware Cloud Foundation stack, using Python and Selenium. A procedure that took three to four hours of stepping through routines by hand became roughly 30 minutes running unattended, and it eliminated most of the physical trips to the server room to check cluster status. I also interfaced with C++ kernel code in the bare-metal hypervisor and debugged physical server racks when experimental deployments failed to boot.
Service
I was a member of the Tau Beta Pi Michigan Gamma Chapter from 2022 to 2024, and served on the University of Michigan Engineering Student Government's Student Life Committee from 2020 to 2022.
Personal
The Leland Stanford Junior University Marching Band has been a significant part of my time at Stanford ever since I joined in the fall of 2024, and I play marching drums, the glockenspiel, and the piccolo in the band. I have also served on the band's Props and Uniforms staff since March 2025. It is a place where, paradoxically, I find a sense of myself in the chaos and insanity the band is known for.
In terms of competitive team sports, I was a member of the University of Michigan Club Cycling Team from 2021 to 2023.
When it comes to slightly more fringe and frivolous interests, I have also been incredibly invested in the Touhou Project game series out of Japan. Try to catch me at an anime convention near you if you can!
Contact
The best way to reach me is by email at peli@stanford.edu. I finish my M.S. in December 2026 and will be available for full-time work from approximately February 2027. I am looking for industry roles in hardware formal and design verification, compiler engineering, and performance engineering.
You can also find me on GitHub, LinkedIn, and Google Scholar.