Projects

Three systems that between them cover the path I care about: measure what a workload actually does with memory, prove what the best placement for it is, and put the result on silicon.

GainSight — data lifetime profiling for heterogeneous on-chip memory

Research project, first author and lead developer

An open-source framework that extracts cycle-accurate data lifetimes from accelerator workloads and turns them into optimal heterogeneous on-chip memory compositions.

Flan — solver-backed memory placement in MLIR

Research project, originator and lead

A compiler framework that formulates data placement across heterogeneous memory as an Optimization Modulo Theories problem and solves it with Z3, producing provably optimal placement schedules instead of hand-written heuristics.

GEMMA — 16nm AI accelerator tapeout

Silicon project, memory and design-for-test blocks

A 16nm AI accelerator taped out with an embedded DRAM partition, design-for-test module, and refresh controller I redesigned in the four months before tapeout.

Coursework and academic projects are on the Academics page, and papers are on the Research page.